Signed, unsigned and std_logic_vector

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  1. Your rule 3: "Always use std_logic_vector for your ports. Do not use signed or unsigned ports." was introduced for VHDL designs with mixed arithmetic library environments. as long as all design units use ieee.numeric_std no problems will arise. It might be noted in your post.

    The graphic misses 2 conversions from signed to unsigned and reverse. Maybe that's because this graphic was not drawn by yourself...

    You should add a proper citation to your images, otherwise you would claim that image was drawn by yourself. Here is at least one other (older) source.
    http://www.bitweenie.com/listings/vhdl-type-conversion/
    by Shannon Hilbert, 10.02.2013

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    1. Hi Patrick,

      As usual, thanks for your many insightful comments.

      As for the image, it has appeared so many times, and in so many versions, that I don't think I can really find an attribution for it. Since you have seen many of my posts you must have noticed I ALWAYS give attribution for them. For this image it is really difficult to do, since its versions go as far back as 2001. Anyway, I will add the casting from unsigned to signed and viceversa.

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    2. I highly appreciate your work for the VHDL community!

      You can cite any of the other authors, but a better solution is to cite the oldest publication you can find.

      Another solution is to (re-)draw such simple images yourself. In a scientific context, you would even need to cite the original image author when you redraw an image because the first idea on how to present the content originates to that author :).

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