Signed, unsigned and std_logic_vector

VHDL is a strong typed language. It is also a language which has quite a long history. These two facts together make handling of signed and unsigned numbers quite confusing. Even today I see lots of code examples with incorrect treatment of signed and unsigned arithmetic.
Part of the history of the VHDL language is the std_logic_arith library. This library is a non-standard library, or maybe I should say de-facto standard library, created by Sinopsis. I recommend not to use it, since there is an ieee library for arithmetic operations today, ieee.numeric.
Adding to the confusion is the fact of how operations are made for binary coded numbers. Unsigned numbers represent natural number from zero to the maximum number that can be coded in the vector. If we use 8-bit vectors, we will be able to code values between 0-255. To represent signed numbers, one popular format is two's complement. Using two's-complement we can code numbers from -128 to 127 in an eight bit vector.
Unless told beforehand, VHDL has to know if a number is signed or unsigned. I will give you what I think are MUSTs and also some recommendations to work with number and avoid pitfalls.
  • Use ieee.numeric_std. DO NOT use std_logic_arith.
  • DO NOT use the signed or unsigned libraries. When you use these libraries, all the std_logic_vector arrays in the file are considered signed or unsigned by default. This can cause very difficult to track bugs.
  • Always use std_logic_vector for your ports. Do not use signed or unsigned ports.
  • Signals that should be treated as signed or unsigned are EXPLICITLY declared as such in your source file. If the signals are ports, they are converted back and forth to std_logic_vector inside each source file.
  • integer fasten simulations. However, I must admit that I am not used to them. I use std_logic_vector, signed and unsigned as required. Of course, if a specific vector is used as an index to an array, it must be converted to integer first.
  • Once you stick to numeric_std, the following figure explains all the transitions from each type to the other:

Comments

  1. Your rule 3: "Always use std_logic_vector for your ports. Do not use signed or unsigned ports." was introduced for VHDL designs with mixed arithmetic library environments. as long as all design units use ieee.numeric_std no problems will arise. It might be noted in your post.

    The graphic misses 2 conversions from signed to unsigned and reverse. Maybe that's because this graphic was not drawn by yourself...

    You should add a proper citation to your images, otherwise you would claim that image was drawn by yourself. Here is at least one other (older) source.
    http://www.bitweenie.com/listings/vhdl-type-conversion/
    by Shannon Hilbert, 10.02.2013

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    Replies
    1. Hi Patrick,

      As usual, thanks for your many insightful comments.

      As for the image, it has appeared so many times, and in so many versions, that I don't think I can really find an attribution for it. Since you have seen many of my posts you must have noticed I ALWAYS give attribution for them. For this image it is really difficult to do, since its versions go as far back as 2001. Anyway, I will add the casting from unsigned to signed and viceversa.

      Delete
    2. I highly appreciate your work for the VHDL community!

      You can cite any of the other authors, but a better solution is to cite the oldest publication you can find.

      Another solution is to (re-)draw such simple images yourself. In a scientific context, you would even need to cite the original image author when you redraw an image because the first idea on how to present the content originates to that author :).

      Delete

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