VHDL component vs. entity


A VHDL Entity defines the interface of a design unit. The elements of an entity are:
  • Name of the entity
  • Generic parameters
  • Ports (connections of the entity)
    • Most popular ports are of type in, out, and inout.
The architecture specifies the behavior of an entity. An entity can be bonded to several architectures. Each architecture sees all the elements (ports, parameters) of the entity.
component consists of an entity and architecture pair. A component must first be declared. The declaration is a 'virtual' action, a declared component still isn't doing nothing.


For a component to exercise its capabilities, it must be instantiated. The instantiation of a component is compared, many times, to the act of connecting a physical chip to its socket. A component can be instantiated multiple times in a design.
A component can be instantiated without a component declaration. Many designers prefer this approach, which was introduced on VHDL '93 (direct instantiation), reducing the redundancy and the need to update parameters and ports in two different places (in the declaration part and in the instantiation part).

Comments

  1. A component can have different generic values than it's entity. No one volunteered to improved components and configurations for VHDL-2017. I hope I can help to improve it for VHDL-2020.

    ReplyDelete

Post a Comment

Popular posts from this blog

VHDL or Verilog?

Pseudo random number generator Tutorial

FPGA internal tri-state buses