FPGA internal tri-state buses

Block RAM memory - Source: Xilinx

This post is now hosted here

Comments

  1. I designed a compact single bus(control unit arbitrated) processor with a few friends of mine last year , alll worked well at the sumilation level , us forcing the bus to a high impedance state when not being used. We got the shocker the evening when we finished the design as we did our first synthesis run - no tri state buses inside the Atrix 7 Fpga`s , We spent the rest of the night creating seperate input & outputs for each device on the bus and had to introduce a seperate bus arbitrator module. So much for a neat and compact design :P

    ReplyDelete
  2. You can program the project with tristates if it is convinient. And the project will be very well. The fact is that the synthesizer substitutes these tristates to the wires and multiplexer.

    ReplyDelete

Post a Comment

Popular posts from this blog

Xilinx AXI Stream tutorial - Part 1

Analysis, elaboration and synthesis